1. Field of the Invention
The present invention relates generally to methods of semiconductor wafer fabrication, and more particularly, to a method of arranging a semiconductor wafer within a photolithography tool.
2. Description of the Related Art
The following descriptions and examples are given as background information only.
A technique known as “photolithography” or simply “lithography” is often used to pattern the various levels of an integrated circuit. In general, photolithography entails transferring an optical image from a patterned mask plate (i.e., a reticle) to a photosensitive film (i.e., a photoresist) formed upon a substrate. In particular, radiation is transmitted through transparent portions of the mask plate to alter the photochemical reaction of exposed regions of the photoresist and a solvent is used to remove the areas of higher solubility within the resist. The resulting patterned resist film serves to protect underlying conductive and/or dielectric materials within a semiconductor topography from subsequent etching and/or ion implantation processes. A typical process flow for manufacturing a semiconductor device includes twenty or more lithography steps. Thus, lithography processes and tools have been a focus for continuing the reduction of feature sizes within the semiconductor fabrication industry.
Alignment of successive layers in an integrated circuit is important to ensure proper operation of the circuit. As such, a patterned mask plate must be properly aligned to previously formed features in a semiconductor topography during a lithography process in order to avoid operational malfunctions, such as but not limited to shorting between structures that should be isolated from each other and/or shorting between isolation of structures that should be coupled to each other. Typically, an alignment system is used within a photolithography tool to align the mask plate to the semiconductor topography. The alignment system may employ alignment marks formed in the substrate (e.g., trenches in the form of a geometric shape, such as a square, a “+” or an “X”) as reference points to align the mask plate to the semiconductor topography. One technique of aligning a reticle to a wafer includes propagating a light beam through a projection lens of the system to locate alignment marks. Such an approach is often referred to as “through the lens” or “on-axis.” In most cases, the light beam in an on-axis alignment unit is not usually the same wavelength as the exposure wavelength used to produce the chemical reaction with the photoresist. Consequently, there is often a discrepancy between alignment readings of the alignment system and exposure system. Such discrepancies are increasing as semiconductor features continue to get smaller with new generations of technology. In particular, smaller exposure wavelengths used to produce smaller features and the need for more accurate alignment has increased with smaller features, rendering on-axis alignment systems inadequate for some processes.
One alignment technique which employs wavelengths closer to and, in some embodiments, the same wavelength used in exposure units propagates light to find and correlate the position of wafer alignment marks and wafer stage marks. The propagation of light is not through the projection lens and, therefore, is often referred to as “off-axis” alignment. A greater broad band of light can be used with off-axis alignment systems and, as a benefit, such systems generally have a greater capability of detecting wafer marks within different film thicknesses. Until recently, photolithography tools employing on-axis alignment (hereinafter referred to as on-axis photolithography tools) were sufficient to align reticles to wafers and, therefore, were the most commonly used tools within the industry. As feature sizes within semiconductor devices continue to decrease, however, the use of photolithography tools employing off-axis alignment (hereinafter referred to as off-axis photolithography tools) is becoming more prevalent. Since sizes of semiconductor features differ within an integrated circuit, some fabrication facilities utilize both on-axis and off-axis photolithography tools in order to evade costs of converting all photolithography tools to off-axis systems.
Regardless of the type of alignment process used, alignment marks need to be visible throughout the fabrication process, either through surface topology contrast or by viewing them through transparent layers of the semiconductor topography. Maintaining visibility of alignment marks from the topside of a wafer, however, can be difficult during or after deposition of opaque layers following planarization of an underlying layer. As such, alignment marks are sometimes aligned with shadow clamps configured to cover portions of the wafer in deposition chambers and, therefore, avoid deposition of films thereon. Shadow clamps are typically fixed and, therefore, alignment marks are often configured having a similar spatial arrangement as shadow clamps. In addition, since wafers are typically positioned within deposition chambers with respect to crystal orientation markers of the semiconductor wafers, alignment marks are generally printed in the same relative arrangement to crystal orientation markers as shadow clamps. Yet an alternative approach to viewing alignment marks from the topside of a semiconductor wafer to align the wafer within a photolithography tool is to view the alignment marks from the bottom side of the wafer, obviating the need for shadow clamps.
Alignment marks in some off-axis photolithography tools, however, cannot be accessed from the underside of a semiconductor wafer due to stage movement limitations. In addition, some off-axis photolithography tools include areas which prohibit alignment mark detection above a wafer. Thus, alignment of a semiconductor wafer in an off-axis photolithography tool may be difficult or impossible in some cases, particularly in embodiments in which alignment marks are positioned within the regions which prohibit detection of alignment marks above the wafer. As such, sometimes further provisions need to be taken to insure proper alignment of a wafer in an off-axis photolithography tool. For example, additional alignment marks may be printed within areas accessible for detection by an off-axis photolithography tool. The printing of such alignment marks, however, undesirably increases the costs and process time of wafer fabrication as well as decreases the available space wafer upon which to form semiconductor devices. Moreover, the formation of additional alignment marks necessitates installation of additional shadow clamps, resulting in major interruptions to the fabrication operation to retrofit the tools.
Accordingly, there is a need for a method of aligning wafers within off-axis lithography tools without adding further alignment marks on the wafers. It would be beneficial for such a method to use alignment marks positioned with respect to locations of shadow clamps in deposition chambers. In addition, it would be advantageous for such a method to be compatible for fabrication sequences which utilize on-axis photolithography tools as well off-axis photolithography tools.